This invention relates generally to the field of data processing systems, and more particularly, to data processing systems that schedule the execution of selected requests to increase the performance of the system.
Most modem data processing systems include at least a processor and a memory. The processor is typically connected to the memory by a system bus or the like. Other system components may also be connected to the system bus including, for example, I/O modules, other processors, and/or other memory devices. During normal functional operation of the system, the processor typically executes a series of commands to accomplish a desired result. Some of these commands can result in read requests and write requests to the memory and are typically issued in the order of processor execution.
A read request typically provides a read address to the memory over the system bus. The memory reads the requested data from the location identified by the read address and returns the data to the processor for subsequent processing. Typically, the processor cannot process further commands until the processor receives the return data. In contrast, a write request typically provides a write address and write data packet to the memory over the system bus. The memory writes the write data to the write address. For a write request, no return data is typically expected, and thus, the processor can continue processing further commands immediately after the write request is provided to the system bus and/or memory. In many systems, the system bus operates at a lower speed than the processor. In addition, more than one system component may use the system bus and/or memory. For these and other reasons, the read and write requests issued by the processor may not be immediately serviced by the memory, thereby reducing the performance of the system.
To help alleviate this bottleneck, a write queue can be provided between the processor and the system bus to increase the speed at which the processor can issue write requests. As indicated above, no return data is typically expected from a write request, and thus the processor can continue processing further commands immediately after the write request is provided to the system bus and/or memory. The write queue is used to temporarily store write requests that are provided by the processor until the memory and/or system bus can service the write requests. This frees up the processor more quickly because the write queue, rather than the processor, waits for the system bus and/or memory to service the write request.
U.S. Pat. No. 5,790,813 to Wittaker discloses a pre-arbitration system and look-around circuit for increasing the throughput of a data processing system by allowing read requests to be executed prior to previously issued write requests so long as the data coherency of the system is not compromised. As noted above, read requests can slow processor throughput by not allowing the processor to process further commands until the read data is returned from the memory. Write requests, on the other hand, typically do not prevent the processor from processing further commands after the write request is issued. Thus, by assigning a higher priority to read requests relative to write requests, Wittaker suggests that the overall throughput of the data processing system may be increased.
Some data processing systems are configured such that the execution of two or more request types is faster when the requests are executed in a particular sequence. For example, the execution of two read requests followed by two write requests may be faster than the execution of a read, a write, a read, and finally a write request. In some systems, it is the transition from one request type to another that introduces a delay in the system. Therefore, it has been found that it may be more efficient to execute a string of a first request type followed by a string of another request type. Simply assigning a priority to one of the request types relative to the other request type, as suggested by Wittaker, typically will not provide the desired sequence of two or more different request types. Thus, it would be desirable to provide a data processing system that can schedule the execution of selected requests such that two or more request types are executed in a particular predetermined sequence to achieve increased system performance.